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MR0A08B
Table 12 – Write Cycle Timing 3 (Shortened t WHAX , W and E Controlled)
Parameter 1 Symbol Min Max
Unit
Write cycle time 2
Address set-up time
Address valid to end of write ( G high)
Address valid to end of write ( G low)
Write pulse width
Data valid to end of write
Data hold time
Enable recovery time
Write recovery time 3
Write to enable recovery time 3
tAVAV
tAVWL
tAVWH
tAVWH
tWLWH
tWLEH
tDVWH
tWHDX
tEHAX
tWHAX
tWHEL
35
0
18
20
15
10
0
-2
6
12
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1.
2.
3.
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or
after W goes low, the output will remain in a high impedance state. After W, or E has been brought high, the signal must re-
main in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
If E goes low at the same time or after W goes low the output will remain in a high impedance state. If E goes high at the
same time or before W goes high the output will remain in a high impedance state. E must be brought high each cycle.
Figure 10 – Write Cycle Timing 3 (Shortened t WHAX , W and E Controlled)
t AVAV
A (ADDRESS)
E (CHIP ENABLE)
t AVWH
t WHAX
t EHAX
t WLEH
W (WRITE ENABLE)
D (DATA IN)
Copyright ? 2013 Everspin Technologies
t AVWL
17
t WLWH
t DVWH
t WHEL
t WHDX
MR0A08B Rev. 8, 10/2013
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